Sequential Operating Simulation of Solid State Transformer-Driven Next-Generation 800 VDC Data Center

Overview

The work is a 2026 arXiv preprint by Jian Xu and colleagues (arXiv:2601.16502). It models a solid state transformer (SST) fed 800 VDC data center supply (10 kV MVAC to 800 VDC via a three-phase H-bridge rectifier plus a dual-active-bridge stage) on an RTDS real-time simulator. It compares this with a conventional double-conversion UPS chain using measured day- and month-long AI and conventional IT load profiles.

The study reports DC-bus regulation, input-side losses, low-frequency power spectra at the grid interface and a DC-link capacitance sensitivity study. The measured 24 h AI cluster profile included down-ramps of 23.2% and up-ramps of 24.4%; the 800 VDC bus stayed within ±2% of rated voltage 100% of the time. On energy, over 30 days the average input loss was 1.924% for the SST architecture versus 9.553% for the modelled UPS architecture, so the SST drew roughly 8.5% less energy from the grid.

Monthly, the SST used about 26.36 MWh less than the UPS chain for AI load (about 9.0%) and about 20.90 MWh less for conventional IT load (about 7.27%). The SST loss ratio stayed close to 2%, while the UPS chain loss ratio ranged about 7%-13% and peaked during high demand. The UPS-based supply showed sharp low-frequency peaks in the grid-side power spectrum, whereas the SST flattened the 0.1 Hz to a few Hz band.

In the DAB low-voltage capacitance sweep (30-60 µF), load-side ripple fell sharply up to about 55 µF, and 0.1-3 Hz input-power oscillation energy was lowest around 50-60 µF, with no noticeable efficiency penalty. An important limit is that the UPS baseline loss figures are high relative to modern UPS datasheets, so the saving percentages should be read as specific to the modelled chains.

Key points

1. The measured 24 h AI cluster profile included down-ramps of 23.2% and up-ramps of 24.4%; the 800 VDC bus stayed within ±2% of rated voltage 100% of the time.
2. Over 30 days the average input loss was 1.924% for the SST versus 9.553% for the modelled UPS architecture; the SST drew roughly 8.5% less energy from the grid.
3. Monthly, the SST used about 26.36 MWh less than the UPS chain for AI load (about 9.0%) and about 20.90 MWh less for conventional IT load (about 7.27%).
4. The SST loss ratio stayed close to 2%, while the UPS chain loss ratio ranged about 7%-13% and peaked during high demand.
5. The UPS-based supply showed sharp low-frequency peaks in the grid-side spectrum; the SST flattened the 0.1 Hz to a few Hz band.
6. In the DAB capacitance sweep (30-60 µF), ripple fell sharply up to about 55 µF and 0.1-3 Hz oscillation energy was lowest around 50-60 µF, with no noticeable efficiency penalty.
7. UPS baseline losses are high relative to modern UPS datasheets; savings are specific to the modelled chains.

Using it in design

• Offer an SST/800 VDC front end as an alternative architecture template next to transformer + UPS, with its efficiency curve as a catalogue field.
• Because reported savings depend on the UPS baseline, compare architectures using the user's actual UPS and transformer efficiency curves rather than fixed percentages.
• For AI loads, include a grid-interface oscillation and ramp check (MW/min and low-frequency content) in addition to energy.
• Treat DC bus regulation (such as ±2% of rated voltage) against load ramps as a separate design check.
• Treat DC-link capacitance as a sensitivity parameter for oscillation and ripple.

Who should read it

Electrical designers and power electronics researchers evaluating new medium-voltage-to-DC power architectures for AI loads.

Publication details

Authors

Jian Xu; Xinxiong Jiang; Yi Bao; Yuchen Zheng; Xuhui Chen; Qiang Xu; Siyang Liao; Deping Ke; Xiaoqi Gao

Publisher

arXiv (preprint)

Year

2026

Document number

arXiv:2601.16502

Document language

English

Source type

Scientific

Access

Free to read

DOI

10.48550/arXiv.2601.16502

Licence

arXiv distribution permission — reuse conditions remain with the rights holder

Citation