How AI Load Swings Reduce Datacenter Power Conversion Efficiency

Overview

This short technical note by Heetarth Joshi, Ali Alenezi, Fang Chen Lin, Prasad Enjeti, Xiaoyang Wang and Xin Chen (arXiv:2610.33300, 2026) quantifies how the compute/communicate power swing of AI workloads degrades the efficiency of cascaded rack power conversion. It is an arXiv preprint, not a peer-reviewed publication. The method uses manufacturer efficiency curves for a GaN PFC stage (240 VAC to 400 VDC), an LLC stage (400 V to 51 V) and point-of-load (POL) stages (48 V to 1 V).

The authors apply an energy-based, cycle-averaged efficiency formula to a 1 Hz, 50% duty square-wave load. The formula is (D*PH + (1-D)*PL) / (D*PH/etaH + (1-D)*PL/etaL). The result is that efficiency evaluated at the average load overstates the real efficiency, and the penalty grows with each load-dependent conversion stage. In the example, for a load swinging between 5 kW and 510 W the 240 VAC-to-51 VDC path efficiency falls to 95.97% versus 96.82% at the equivalent constant average load (0.88% loss).

Including 48 V-to-1 V POL conversion, cycle efficiency is 89.45% versus 90.96% at the constant 2755 W average load, a 1.66% reduction. Cascaded system efficiency at 5000 W chip power is 90.35% but only 81.55% at 510 W. As a limit, grid-side transformer and UPS losses were excluded; the authors state that including them would add further losses from fluctuating AI loads. The note is a short analysis limited to one load profile and manufacturer curves.

Key points

1. For a 1 Hz, 50% duty load swinging between 5 kW and 510 W, the 240 VAC-to-51 VDC path efficiency falls to 95.97% versus 96.82% at the equivalent constant average load (0.88% loss).
2. Including 48 V-to-1 V POL conversion, cycle efficiency is 89.45% versus 90.96% at the constant 2755 W average load, a 1.66% reduction.
3. Cascaded system efficiency at 5000 W chip power is 90.35% but only 81.55% at 510 W (POL 90%, DC-DC 94.05%, AC-DC 96.35% at low load).
4. Cycle efficiency is computed as (D*PH + (1-D)*PL) / (D*PH/etaH + (1-D)*PL/etaL).
5. Grid-side transformer and UPS losses were excluded; the authors state including them would add further losses from fluctuating AI loads.
6. Efficiency evaluated at the average load overstates real efficiency; the penalty grows with each load-dependent conversion stage.

Using it in design

• In power-chain loss calculators for AI halls, do not evaluate PSU, UPS and transformer efficiency only at average load; accept a load-profile descriptor (duty cycle, high/low power, frequency).
• Compute an energy-weighted cycle efficiency per stage using part-load efficiency curves from the catalog.
• Store full efficiency-vs-load curves, not just a single peak value, for PSUs, rectifiers, UPS and DC-DC stages.
• Warn when a training workload pushes stages into their low-load region.
• Feed the extra loss (about 1-2%) into the heat load and PUE estimates.

Who should read it

Electrical engineers designing the power chain of AI halls, those selecting UPS and PSUs and developers of efficiency calculators.

Publication details

Authors

Heetarth Joshi; Ali Alenezi; Fang Chen Lin; Prasad Enjeti; Xiaoyang Wang; Xin Chen

Publisher

arXiv preprint (Texas A&M University)

Year

2026

Document number

arXiv:2610.33300

Document language

English

Source type

Scientific

Access

Free to read

DOI

10.48550/arXiv.2610.33300

Licence

arXiv distribution permission — reuse conditions remain with the rights holder

Citation