Preventing arc flash incidents by design

Overview

In this 2012 article in Consulting-Specifying Engineer, Bruce W. Young explains the drivers of arc-flash incident energy: available fault current and protective device characteristics. He then shows how labelling, maintenance settings and design choices reduce the hazard in critical facilities. The article is practice-oriented engineering writing, not a standard. The article therefore offers designers a way to reduce the hazard at design stage rather than after the calculation.

It starts from hazard and injury data: incident energy above 1.2 cal/cm2 can cause second-degree burns, and IEEE 1584 suggests a 2 s maximum arcing exposure time. Higher available fault current can reduce hazard because it shortens device clearing time. A main device may need separate line-side and load-side labels because its line side stays energized when open. Dual power paths let equipment be fully de-energized for work while operations continue.

The worked example is a 1,600 A, 480 V solid-state trip breaker. With coordinated settings, clearing takes about 13-19 s, the boundary is 105 in. and incident energy is 22 cal/cm2 (Category 3); with temporary maintenance settings it falls to 0.02 s, 15 in. and 0.86 cal/cm2. The author cautions that changing settings can nuisance-trip critical loads. A field incident on a 20-year-old switchboard illustrates the danger of forcing equipment that will not operate.

Key points

1. Incident energy above 1.2 cal/cm2 can cause second-degree burns; IEEE 1584 suggests a 2 s maximum arcing exposure time.
2. Higher available fault current can reduce hazard because it shortens device clearing time.
3. A main device may need separate line-side and load-side labels because its line side stays energized when open.
4. 1,600 A/480 V example: coordinated settings give about 13-19 s clearing, 105 in. boundary, 22 cal/cm2 (Category 3); maintenance settings give 0.02 s, 15 in., 0.86 cal/cm2.
5. Dual power paths let equipment be fully de-energized for work while operations continue.
6. Changing settings can nuisance-trip critical loads.

Using it in design

• Arc-flash outputs should label both line and load sides of mains and compare normal versus maintenance-mode settings.
• Recommend maintenance switches or ERMS on large LV mains.
• Recommend dual-path topologies so work can be done de-energized.
• Record in the report the risk that maintenance settings may nuisance-trip critical loads.

Who should read it

Data centre electrical designers, engineers who run protection and selectivity studies and maintenance managers.

Related standards

• NFPA 70E
• IEEE 1584

Publication details

Authors

Bruce W. Young

Publisher

Consulting-Specifying Engineer

Year

2012

Document language

English

Source type

Expert / community

Access

Free to read

Licence

Copyright retained; citation only — the publisher’s terms apply to the original document

Citation